FIG. 1 is a schematic view of a mobile telephone having a receiver E and a transmitter S which are connected to an antenna A. The mobile telephone receives, from a base station, data frames (frames F) which are output by the receiver E for further data processing by a downstream data processing unit DV. The transmission channel for transmitting the data frames is exposed under certain circumstances to severe interference, in particular in the case of mobile radio telephony so that the data frames F are, under certain conditions, received in a highly falsified state by the mobile telephone. If the decoding of the received data frame F reveals that it is errored, the mobile telephone transmits an automatic request signal ARQ to the base station for the renewed transmission of the data frame F.
FIG. 2 shows a flowchart of the ARQ2 method such as is used in EGPRS receivers according to the prior art. GPRS (=general packet radio service) refers to data transmission according to X.25 standard using GSM (GSM: Global System for Mobile Communications). EGPRS receivers are GPRS receivers using what is referred to as the EDGE modulation method.
In a step S1 the data frames F are received by the mobile telephone by means of a radio frequency receiver and a demodulator.
Then, in a step S2, the channel equalization of the received data frame is carried out by means of an equalizer.
The received data frame contains signaling data and information data. In a step S3, the signaling data and the information data are separated from one another by means of a separator circuit of the receiver E. The received signaling data contains here a data frame identifier and a decoder instruction for the decoding of the respective information data.
In a step S4, the separated-off received signaling data is decoded by means of a channel decoding circuit, the decoded signaling data containing the decoding instruction for decoding the respective information data.
In a step S5, the channel decoding circuit checks whether or not the decoding of the signaling data has taken place without error.
If the decoding of the received signaling data has not been carried out without error [lacuna] the channel decoding circuit, the sequence returns to step S1 and the next received data frame F is processed.
If conversely it is determined in step S5 that the decoding of the signaling data has been carried out without error by the channel decoding circuit, the received information data and the decoding instruction, contained in the decoded signaling data, for the decoding of the received information data are stored in a system memory of a baseband control unit in a step S6 by means of a memory controller of an RLC/MAC control circuit.
In a step S7, the RCL/MAC control circuit uses its memory controller to search through all the buffered received information data which has the same packet number or data frame identifier, and reads the latter out of the system memory. The read-out information data is fed to an information data decoder for the decoding of the information data in accordance with the decoding instruction.
In a step S8, the read-out information data is decoded by the information data decoder in accordance with the decoding instruction for the decoding of the information data. For this purpose, the information data decoder receives the corresponding information data decoding instruction from a data decoding controller contained in the RLC/MAC control circuit. The RLC/MAC control circuit receives, for its part, the decoding instruction for the decoding of the information data from a signaling data decoder.
In a step S9, the information data decoder checks whether or not the decoding of the information data has taken place without error, and outputs a corresponding indicator signal to the RLC/MAC control circuit.
If the decoding of the information data has been carried out without error by the information data decoder, the RLC/MAC control circuit outputs a control signal to the information data decoder for the transmission of the decoded information data to a downstream LLC circuit (LLC: Logic Link Control). At the same time, all the information data buffered in the system memory together with the associated data frame identifier or packet number is cleared from the RLC memory area of the system memory.
If, in step S9, the information data decoder detects that the decoding of the information data has not taken place without error, the information data which has been decoded in an errored fashion is not transmitted to the downstream LLC circuit, and the received [lacuna]. The information data buffered in the system memory is not cleared from the RLC memory area of the system memory and remains in the memory. In addition, the RLC/MAC control circuit outputs a control signal to the transmitter of the mobile telephone, which transmitter requests the incorrectly decoded data frame again with the respective data frame identifier by means of a request signal (ARQ) which has been output to the base station.
The process then returns to step S1.
FIG. 3 shows an EGPRS receiver according to the prior art, in which the ARQ2 method illustrated in FIG. 2 is carried out. The receiver has an antenna A for receiving the transmitted data frames, and a downstream signal conditioning circuit. In the signal conditioning circuit, the data frames which have been transmitted in analog form are demodulated by means of an RF demodulation circuit and are fed to a downstream analog bandpass filter bank for frequency band selection. An analog/digital converter for converting the demodulated data frames and digital data frames is connected downstream of the bandpass filter bank.
The digital data frames are fed to a digital equalizer for equalizing the data which is transmitted on the transmission channel.
At the output end, a data separator circuit which separates the signaling data contained in the data frame from the information data which is also contained in the data frame is connected downstream of the equalizer. The signaling data is fed via the separator circuit to a signaling data decoder via data lines. The signaling data decoder, the data separator circuit and the equalizer are integrated into a digital signal processor (DSP) here. The signaling data decoder decodes the received signaling data in accordance with a predefined decoding instruction for the decoding of signaling data and outputs the decoded signaling data to the RLC/MAC control circuit via data lines. At the same time, the signaling data decoder determines whether or not the decoding of the signaling data has taken place without error. This determination is made by means of redundant data which is contained in the signaling data. Via a control line, the signaling data decoder outputs, to the RLC/MAC control circuit a corresponding indicator signal which indicates the error-free or errored decoding of the signaling data of a data frame.
If the indicator signal which is received by the signaling data decoder indicates that the decoding of the signaling data has taken place without error, the information data—separated off by the separator circuit—of the associated data frame and the decoded decoding instruction for decoding the information data are written into the RLC memory area of the system memory by the memory controller of the RLC/MAC control circuit. Then, the memory controller of the RLC/MAC control circuit searches through all the buffered information data which is associated with the data frame with the same data frame identifier and is located in the RLC memory area of the system memory, and reads this information data out from the system memory. The read-out information data is fed via data lines to the information data decoder of the baseband control unit. The information data decoder decodes all the supplied information data which has the same frame identifier. In the process, the information data decoder checks whether or not the decoding of the information data has taken place without error with respect to the data instruction, supplied by the data decoder/control circuit, for the decoding of information data. The information data decoder outputs an indicator signal to the data decoder controller of the RLC/MAC control circuit via an indicator line, which indicator signal indicates whether or not the decoding of the information data has taken place successfully. If the received indicator signal indicates that the decoding of the information data by the information data decoder has been terminated successfully, the data decoding controller outputs a control signal to the information data decoder, by means of which control signal the information data decoder receives the instruction to pass on the decoded information data to the downstream LLC block. In addition, the memory controller of the RLC/MAC control circuit outputs a control signal to the system memory by means of which the information data which is buffered in the RLC memory area and which has been decoded without error by the information data decoder is cleared.
If, conversely, the indicator signal which has been output by the information data decoder indicates that the information data of the data frame has not been decoded without error, the data decoding controller outputs a control signal to the information data decoder which prevents the information data which has been decoded in an errored fashion from being passed on to the downstream LLC block. The encoded information data which is buffered in the RLC memory area and which has not been successfully decoded by the information data decoder is not cleared. In addition, the RLC/MAC control circuit outputs a control signal to a transmitter which sends off a request signal ARQ to the base station to request the renewed transmission of the data frame.
The receiver according to the prior art which is shown in FIG. 3 has a signaling data decoder which is integrated into the DSP processor, and an information data decoder which is integrated into the baseband control unit. The signaling data decoder and the information data decoder are provided for decoding different data, namely on the one hand decoding signaling data and on the other hand decoding information data, but the functionality of the two decoders in terms of circuitry is the same. However, the expenditure on circuitry to implement the signaling data decoder and the information data decoder is very high.
The disadvantage of the circuit arrangement according to the prior art which is illustrated in FIG. 3 is that two data decoders have to be provided, and the expenditure in terms of circuitry for the receiver is thus very high overall.